版权说明 操作指南
首页 > 成果 > 详情

Design and Realization of Multi-port Register File based on Schematic Diagram

认领
导出
反馈
分享
QQ微信 微博
成果类型:
会议论文
作者:
Jiang, Lihua*;Zuo, Cuihua
通讯作者:
Jiang, Lihua
作者机构:
[Zuo, Cuihua; Jiang, Lihua] Wuhan Polytech Univ, Dept Comp, Wuhan, Hubei, Peoples R China.
通讯机构:
[Jiang, Lihua] W
Wuhan Polytech Univ, Dept Comp, Wuhan, Hubei, Peoples R China.
语种:
英文
关键词:
Multi-port register file;Schematic;Programmable logic device;FPGA
期刊:
PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON ELECTRONIC, MECHANICAL, INFORMATION AND MANAGEMENT SOCIETY (EMIM)
ISSN:
2352-538X
年:
2016
卷:
40
页码:
631-636
会议名称:
6th International Conference on Electronic, Mechanical, Information and Management Society (EMIM)
会议论文集名称:
ACSR-Advances in Comptuer Science Research
会议时间:
APR 01-03, 2016
会议地点:
Shenyang, PEOPLES R CHINA
会议主办单位:
[Jiang, Lihua;Zuo, Cuihua] Wuhan Polytech Univ, Dept Comp, Wuhan, Hubei, Peoples R China.
主编:
Jing, W Guiran, C Huiyu, Z
出版地:
29 AVENUE LAVMIERE, PARIS, 75019, FRANCE
出版者:
ATLANTIS PRESS
ISBN:
978-94-6252-176-6
机构署名:
本校为第一且通讯机构
院系归属:
数学与计算机学院
摘要:
In cpu design, the register file is a necessary device which save the instruction and data. In this paper, we propose a design method for multi-port register file design in the environment of single-cycle CPU system based on the MIPS instruction set and according to the characteristics of multi-port register file, and the Schematic is introduced in order to speed up the development cycle. Furthermore, we discuss the consideration and operational principle of design and realization in detail. The simulation results for the part constructed by FPGA are also presented. In this example which provi...

反馈

验证码:
看不清楚,换一个
确定
取消

成果认领

标题:
用户 作者 通讯作者
请选择
请选择
确定
取消

提示

该栏目需要登录且有访问权限才可以访问

如果您有访问权限,请直接 登录访问

如果您没有访问权限,请联系管理员申请开通

管理员联系邮箱:yun@hnwdkj.com