This paper proposes a simple and flexibly customized asynchronous FIFO for SDRAM controller based on FPGA, it solves the problem that the SDRAM controller design is complexed and low reusahle.SDRAM is often used in image preprocessing, and its frequency is very high, so multiple asynchronous FIFO are used for data buffer matching its working frequency.But the control of FIFO is redesigned every time, which is too complicated.The design simplifies the timing control of the SDRAM, which improves the system＇s performance and embeds multi-channel ...
